Method and system for modeling, predicting and optimizing chemical mechanical polishing pad wear and extending pad life

ABSTRACT

A computer implemented system and method for modeling, predicting and optimizing a Chemical Mechanical Polishing (CMP) system for polishing semiconductor wafers and other types of substrates used in the manufacture of integrated circuits. The method and system comprises a pad wear and conditioning model that predicts the polishing effectiveness of each sampling point on the polish pad based upon the polishing pad and substrate parameters, the pressure and speed between the wafer and the polish pad, and on the amount of polishing the point has performed in a simulated CMP hardware configuration using the CMP system recipe settings. The model determines the change in pad roughness and thickness for each sampling point on the pad. The model results are used along with wafer scale uniformity and feature scale planarity model results to optimize pad life and determining optimal recipe settings for the CMP process.

BACKGROUND

This invention relates generally to Chemical Mechanical Polishing (CMP)processes for planarizing and polishing the substrates used in themanufacture of integrated circuits. More particularly, the invention isa method and system for modeling, predicting and optimizing theperformance of the CMP polishing medium, called polishing pads, and thuspredicting pad wear and extending pad life. The present method andsystem integrates uniformity, planarity, and pad conditioning and wearmodels to predict CMP polishing pad performance and then uses theresulting predictions to optimize CMP polishing pad performance andextend pad life.

Chemical mechanical polishing (CMP) is a method of removing materialfrom the surface of semiconductor wafers and other types of substratesused in the manufacture of integrated circuits. For the purposes ofsimplifying the discussion, the term wafer is used to denote theworkpiece undergoing the CMP process. However, other types of substratesthat utilize CMP processes can be used interchangeably with the termwafer. In the CMP process, the semiconductor wafer is placed on a wafercarrier and pressed face-down on a rotating platen holding a polishingpad. The polishing pad typically has two layers: a relatively stiffupper pad and a relatively soft base pad. A slurry with an abrasivematerial (for example, silica particles of size 10-200 nm) held insuspension is dripped onto the rotating platen and pad during polishing.The carrier and platen rotate at variable speeds, typically on the orderof 30 rpm. The number of wafers that may be simultaneously polishedvaries: single-wafer, dual-wafer, and five-headed polishing systemscurrently exist.

The CMP process removes material at the surface of the wafer throughthis combination of mechanical and chemical action. The CMP process isperformed at various stages in the fabrication of devices on asubstrate. The planarization of dielectric (silicon dioxide) layersbetween multilevel metallization steps is one common application. CMP isused to planarize these interlevel dielectric (ILD) materials, whichhave patterns on them that result from being deposited over patternedmetal lines. CMP is also used to polish metal films such as tungsten andcopper by completely removing them except for that which remains intrenches purposely pre-etched in the underlying ILD. The goal of the CMPprocess is to uniformly remove material from the surface of the wafer toachieve wafer-scale uniformity. In silicon dioxide, small features arealso removed to achieve feature-scale planarity. In polishing metalfilms, the CMP process attempts to preserve small features that arepre-etched in the underlying ILD.

Because the CMP polishing pad is a major component in the CMP process,analyzing its changing properties and characteristics throughout thepolishing process is especially important in understanding andpredicting uniformity and planarity of the polished wafer. Since the CMPprocess includes mechanical abrasion of the surface, the polishing padwears rapidly. This is often referred to as pad degradation, whichcorresponds to the gradual decay of removal rate of the material fromthe wafer surface. The decay in removal rate is due to the decrease inroughness of the abrasive surface of the pad as the pad degrades withuse. In order to minimize pad degradation, pad conditioning is usuallyemployed whereby the abrasive surface of the pad is restored, either bymechanical damage to the surface or removal of a thin surface layer.Although this helps to roughen the pad and temporarily restore thematerial removal rate, pad conditioning decreases the thickness of thepad, which in turn decreases pad life. Two key physical propertiesaffect pad life: the thickness of the top pad and the compressibility ofthe base pad, both of which change with use. Repeated use andconditioning reduces the top pad thickness and repeated cyclical loadingreduces the base pad compressibility. Pad thinning results in a reducedplanarization rate, which ultimately ends pad life.

Since the pad degrades over time as it is used for polishing and theremoval rate of the semiconductor material varies based in part on padage and wear, wafer-to-wafer uniformity is difficult to predict. It iseven difficult to achieve and maintain uniform material removal withinthe same wafer because the polishing pad removal rate may not beconstant over the wafer due to changes in pad thickness and roughness.As the pad is conditioned as part of the CMP process, the top layer ofthe pad that contacts the wafer is roughened, meaning material isremoved and the pad becomes thinner and correspondingly less stiff. Thesofter base pad layer of the pad is compressed due to the downforce ofthe wafer and also becomes thinner over time. Changes in the padroughness and thickness may also be due in part to the differencesbetween the polishing action or rate at the center and edge of the waferthat may arise due to a number of factors including wafer asymmetry,non-constant relative pad velocity from the edge of the wafer to thecenter, non-uniform slurry and by-product transport under the wafer,wafer bowing due to pressure, or machine drift in time of any of theseparameters.

Since CMP is now the preferred method of removing material from thesurface of semiconductor wafers and other types of substrates used inthe manufacture of integrated circuits, efforts are continually beingmade to optimize CMP processes. Meaningful CMP optimization mustconsider all factors that are significant in affecting the overallquality of CMP performance including uniformity, planarity, and padconditioning and wear. Historically, uniformity has played the dominantrole in modeling for CMP optimization. Although equally important,planarity has played a secondary role in such optimization. Modelingsystems to simulate and predict the removal rate of features onsemiconductor wafer surfaces polishing to achieve wafer-scale uniformityduring the CMP process presently exist. There also exist modelingsystems to simulate and predict the removal of small features to achievefeature-scale planarity during the CMP process. Even though padconditioning and wear is an important CMP performance metric, accuratelysimulating and predicting pad degradation over time as not been includedin prediction and optimization systems for CMP processes. No presentwafer-scale uniformity or feature scale uniformity modeling systemincorporates a pad conditioning and wear model that accurately simulatesthe physical properties that influence pad degradation. Therefore, thereis no present system that uses wafer-scale uniformity and feature-scaleplanarity models along with a pad conditioning and wear model to improvewafer-scale uniformity and feature-scale planarity predictions and thenutilizes those predictions to optimize the CMP process while achievingimprovements in semiconductor wafer uniformity and planarity. Inaddition, no present system exists that use a pad conditioning and wearmodel in conjunction with the wafer-scale uniformity and feature-scaleplanarity models to predict pad performance and extend polishing padlife, thereby increasing the number of semiconductor wafers or othertypes of substrates that can be chemically-mechanically polished withone polish pad.

SUMMARY

The present invention is a method and system that uses wafer-scaleuniformity and feature-scale planarity models along with a padconditioning and wear model to improve wafer-scale uniformity andfeature-scale planarity predictions. It then utilizes those predictionsto optimize the CMP process to achieve improvements in semiconductorwafer uniformity and planarity. Use of the pad conditioning and wearmodel in conjunction with the wafer-scale uniformity and feature-scaleplanarity models can be used to predict pad performance and extendpolishing pad life. Extending pad life results in an increase in thenumber of semiconductor wafers or other types of substrates that can bepolished with one polishing pad. This can result in significant costsavings in the CMP process, both in reducing the number of pads neededand reduced time for pad replacement.

The pad conditioning and wear model computes and predicts the polishingeffectiveness of each point on the pad based on how much polishing thatpoint has performed. The pad conditioning portion of the model computesthe thickness and roughness of the pad as a function of time andposition on the pad. The kinematics and pressure applied duringconditioning is used to compute the amount of pad material removed ateach point. The pressure distribution between the pad and wafer ismodeled in the pad conditioning and wear model. The total force pushingdown on the wafer carrier is known, and the resulting pressuredistribution between the pad and the wafer may be computed using any ofa number of existing wafer-pad pressure distribution models. Thethickness of the pad is determined by the change in the two pad layersover time. As the top layer is roughened during the conditioningprocess, the top layer becomes thinner and less stiff. As the base layeris compressed due to the pressure by the wafer on the pad, the baselayer becomes thinner and increasingly stiff. The pad wear portion ofthe model computes the pad's roughness, which is represented by aPreston's coefficient, k, that varies with time and position on the pad.The pad conditioning portion of the model computes pad thickness,represented by h, which is also a function of time and position on thepad. The pad conditioning model also computes the restoration of thepad's roughness along with its decrease in thickness.

A wafer scale uniformity model predicts the material removed at eachpoint by using an enhanced Preston equation. Unlike models using thetraditional Preston equation, the enhanced version uses the Prestoncoefficient, k, representing the roughness of the pad which is computedin the pad wear model and varies with time and position on the pad. Whenpolishing first begins, each point on the pad starts with an initialvalue for k. As polishing proceeds, the k value at each point isdecreased depending on the amount of polishing performed by that point.In so doing, the uniformity model now captures the semiconductor wafermaterial rate drop-off commonly observed in CMP processes

A feature-scale planarity model predicts the erosion of features onsemiconductor wafer surfaces using the pad thickness, h, computed in thepad conditioning model that varies with time and position on the pad.The material removal rate predicted by the wafer-scale uniformity modelis used to determine the erosion rate coefficient, E, used in thefeature-scale planarity model. When polishing first begins, the top andbase pad properties for each point on the pad start with an initialvalue. The thickness of the pad is computed in the pad conditioning andwear model and is determined by the change in the two pad layers overtime. Using the pad thickness and roughness computed in the padconditioning model, the feature-scale planarity model predicts howchanges in the top pad thickness and base pad compressibility affectplanarity of the wafer and polishing pad life.

The present invention is a computer implemented method for modeling,predicting and optimizing a Chemical Mechanical Polishing (CMP) systemfor polishing semiconductor wafers and other types of substrates used inthe manufacture of integrated circuits. Polishing pad and semiconductorwafer and substrate parameters are input, a set of pad sampling pointson a CMP polish pad is defined, and the CMP hardware configuration andCMP system recipe settings are simulated. A pad wear and conditioningmodel that predicts the polishing effectiveness of each sampling pointon the polish pad based upon the polishing pad and substrate parameters,the pressure and speed between the wafer and the polish pad, and on theamount of polishing the point has performed in the simulated CMPhardware configuration using the CMP system recipe settings is defined.The pad conditioning and wear model determines the change in padroughness for each sampling point on the pad using a pad wear model anddetermines the change in pad thickness for each sampling point on thepad using a pad conditioning model.

The pad roughness for each sampling point may be represented as a padroughness variable. A set of wafer sampling points on a semiconductorwafer that corresponds to the set of pad sampling points is defined andthe rate of material removed from the wafer at each wafer sampling pointas a function of the pressure and relative speed between the wafer andthe pad at that sampling point is predicted as a function of the padroughness variable at that sampling point.

The pad conditioning model may also represent the polish pad as having arelatively stiff top pad planar surface connected to and located justabove a relatively soft base pad planar surface having a thicknessgreater than the top pad planar surface. The change in the thickness ofthe top pad planar surface for each pad sampling point as a function ofthe polishing pad and substrate parameters, the pressure and speedbetween the wafer and the polish pad, the amount of conditioningperformed on the top pad, and on the amount of polishing the padsampling point has performed in the simulated CMP hardware configurationusing the CMP system recipe settings is computed, and is used todetermine the resulting thickness of the top pad planar surface for eachsampling point. The change in thickness of the base pad planar surfaceas a function of the polishing pad and substrate parameters, thepressure and speed between the wafer and the polish pad, and the amountof polishing the pad sampling point has performed in the simulated CMPhardware configuration using the CMP system recipe settings is computed,and is used to determine the resulting thickness of the base pad planarsurface for each sampling point. The resulting thickness of the top padplanar surface and the base pad planar surface is used to compute a padthickness variable for each sampling point. The predicted change inthickness is used to compute a pad roughness variable, which representsthe roughness of each pad sampling point as a function of the polishingpad and substrate parameters, the pressure and speed between the waferand the polish pad, the amount of conditioning performed on the top padplanar surface, and on the amount of polishing the pad sampling pointhas performed in the simulated CMP hardware configuration using the CMPsystem recipe settings.

A set of wafer sampling points on a semiconductor wafer that correspondsto the set of pad sampling points may be defined. Using the padroughness variable for each pad sampling point as computed in the padwear model as an input to a uniformity model, the material removal rateof the material removed from the surface of a semiconductor wafer ateach wafer sampling point is predicted. The method may further compriseinputting pre-polish wafer topography data, defining a set of wafersampling points on a semiconductor wafer that correspond to the set ofpad sampling points, and using the pad thickness variable for each padsampling point as computed in the pad conditioning model and thematerial removal rate computed in the uniformity model as an input to aplanarity model for predicting the erosion of features on asemiconductor wafer at each wafer sampling point.

The polish pad may be represented as having a relatively stiff top padplanar surface connected to and located just above a relatively softbase pad planar surface with a thickness greater than the top pad planarsurface. The change in the thickness of the top pad planar surface foreach pad sampling point as a function of the polishing pad and substrateparameters, the pressure and speed between the wafer and the polish pad,the amount of conditioning performed on the top pad, and the amount ofpolishing the pad sampling point has performed in the simulated CMPhardware configuration using the CMP system recipe settings ispredicted.

The pad wear model may also calculate a minimum roughness value for thetop pad planar surface of the polish pad, which represents the top pad'sminimum effectiveness in removing material from a semiconductor waferduring the CMP process. A maximum roughness value for the top pad planarsurface of the polish pad, which represents the top pad's maximumeffectiveness in removing material from a semiconductor wafer during theCMP polishing process is also determined. An effective roughness valuefor each sampling point is set to the maximum roughness value uponpolish process initiation. The conditioning process performed on the toppad planar surface to increase the effective roughness value when theroughness value is less than the maximum roughness value and greaterthan or equal to the minimum value is simulated. The effective roughnessvalue for each pad sampling point as it changes during the CMP processand conditioning process is then predicted and updated. The simulationof the conditioning process may further comprise computing a polish wearmodel for each sampling point as a function of a pad degradation ratemultiplied by the effective roughness value for each pad sampling point,times the rate the at work is done on the top pad planar surface by thewafer, where the rate at which work is done is a function of thepressure and speed between the wafer and the polish pad for eachsampling point during the polishing process. The polish wear model isused to calculate the effective roughness value for each sampling pointby computing the difference between the maximum roughness value and theminimum value as a function of the rate at which work is done, and thepad degradation rate over time summed with the minimum effectiveroughness value. The pad degradation rate is set to zero when the padsampling point is not under the wafer.

The pressure distribution between the pad and the wafer is computed andthe pressure between the wafer and the polish pad for each samplingpoint is set to the pressure distribution when the pad is contact withthe wafer

The pad conditioning process may also be modeled by using a padrestoration rate times the effective roughness value for each samplingpoint minus the maximum roughness value, times the rate that work isdone on the top pad surface by the wafer where the rate at which work isdone is a function of the pressure and speed between the wafer and thepolish pad for each sampling point during the polishing process.

In another preferred embodiment, the computer implemented method formodeling, predicting and optimizing a Chemical Mechanical Polishing(CMP) system for polishing semiconductor wafers and other types ofsubstrates used in the manufacture of integrated circuits comprisesinputting polishing pad and semiconductor wafer and substrateparameters; defining a set of pad sampling points on a CMP polish pad;simulating the CMP hardware configuration and inputting CMP systemrecipe settings; using pressure and speed between the wafer and thepolish pad; and defining a pad wear and conditioning model that predictsthe polishing effectiveness of each sampling point on the polish padbased upon the polishing pad and substrate parameters, the pressure andspeed between the wafer and the polish pad, and on the amount ofpolishing the point has performed in the simulated CMP hardwareconfiguration using the CMP system recipe settings. The pad conditioningand wear model determines the change in pad roughness for each samplingpoint on the pad using a pad wear model and the change in pad thicknessfor each sampling point on the pad using a pad conditioning model.Pre-polish wafer topography data is input. A set of wafer samplingpoints on a semiconductor wafer that correspond to the set of padsampling points is defined. The pad roughness for each pad samplingpoint as computed in the pad wear model is input to a uniformity modelfor predicting the material removal rate for the material removed fromthe surface of a semiconductor wafer at each wafer sampling point. Thepad thickness variable for each pad sampling point as computed in thepad conditioning model and the material removal rate computed in theuniformity model is input to a planarity model for predicting theerosion of features on a semiconductor wafer at each wafer samplingpoint. The method may also optimize pad life and determining an optimalCMP recipe setting. The steps of optimizing pad life and determining theoptimal recipe setting may comprise entering performance requirementsfor uniformity, planarity and throughput; forming an optimal recipesolution; modeling the polishing of a set of wafers predictinguniformity, planarity, pad wear, pad conditioning and pad thinning;performing the forming and modeling steps above until the model is notwithin the performance requirements entered; determining the number ofwafers polished and forming a new optimal recipe solution. This processis repeated beginning with the modeling step above until the optimalrecipe solution converges and then the optimal recipe is saved. Theentering of performance requirements for uniformity, planarity andthroughput may be by a user through a graphical user interface or theymay be input from a previous pad conditioning and wear model systemresult. The planarity model may be a two or three dimensional model.

The predicted erosion of features and predicted material removed from asemiconductor wafer at each sampling point to predict polish pad wearand determine optimal CMP system parameters including the optimal padparameters, optimal frequency of pad conditioning, geometry of the CMPhardware configuration and CMP recipe settings may be used to optimizepolish pad life. The optimal settings to enhance polish pad life mayinclude changing polish pad material properties; changing the polish padparameters; determining an optimal frequency of conditioning the top padto maintain constant uniformity; changing the CMP process recipesettings; and varying the simulation of the CMP hardware configuration.Changing the CMP process setting step may include varying the pressurebetween the pad and the wafer during polishing and varying the speedbetween the pad and the wafer during polishing. The optimal settings toenhance polish pad life may be input into the pad conditioning and wearmodel, uniformity model and planarity model to predict the uniformityand planarity of the wafer after the CMP process.

The pad wear and conditioning method may also predict the decay inmaterial removal rate during the CMP polish process and determine theoptimal conditioning frequency of the pad to roughen its surface andrestore the pad's original material removal rate, and determining theoptimal time of pad replacement. Optimizing pad life may also includedetermining an optimal roughness of the polish pad to both extend padlife and achieve a predetermined uniformity of the wafer after the CMPprocess. Optimizing pad life may further include determining an optimaltop pad stiffness and base pad compressibility to both extend pad lifeand achieve a predetermined planarity of the wafer during the CMPprocess.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the presentinvention will become better understood with regard to the followingdescription, appended claims and accompanying drawings where:

FIG. 1 is a system block diagram of the system of modeling, predictingand optimizing Chemical Mechanical Polishing (CMP) pad wear andextending pad life.

FIG. 2A is a side view of a typical Chemical Mechanical Polishing (CMP)tool configuration.

FIG. 2B is a top view of a typical Chemical Mechanical Polishing (CMP)tool configuration.

FIG. 3 depicts the decay in the wafer material removal rate withpolishing time.

FIG. 4 is a flowchart representing the pad wear and conditioning model.

FIG. 5 depicts how the sampling points on a polish pad are interpolatedto determine the Preston coefficient that varies with time and positionon a pad at a wafer sampling point.

FIG. 6 is a cross-section view of the wafer placed face down on thepolish pad during the CMP process.

FIG. 7 is a cross-section view of the wafer and polish pad during theCMP process depicting the spring theory used in the planarity model tosimulate erosion of the wafer.

FIG. 8 depicts a typical display of the results of the planarity model.

FIG. 9 is a flowchart representing pad optimization as performed in thepad wear and conditioning model.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a system block diagram of the system of modeling,predicting and optimizing CMP pad wear and extending pad life. The padconditioning and wear modeling system 100 contains a pad conditioningand wear model 101 that adjusts the polishing effectiveness of eachpoint on the pad based on how much polishing that point has performed.The pressure on the pad 102, pad thickness 103, and rotational speed ofthe pad 112 are input into the pad conditioning and wear model. Pressuredistribution between the pad and wafer is modeled 104. The pressure onthe pad 102 depends upon whether the pad is being conditioned or ispolishing the wafer. When the pad is polishing the wafer, the pressureon the pad is equal to the pressure distribution 104 The padconditioning portion of the model 101 computes top pad thickness andbase pad compressibility to determine the thickness and roughness of thepad as a function of time and position on the pad. The model also tracksthe amount of loading on the base pad to compute its increase instiffness over time. The kinematics, or geometric properties of the padand CMP tool configuration (which is shown in FIGS. 2A and 2B),rotational speed of the pad and pressure distribution duringconditioning is used to compute the amount of pad material removed ateach point. The pad wear portion of the model 101 computes the change inpad roughness due to wear on the pad by the wafer and conditioning ofthe pad. The roughness is represented by a Preston's coefficient thatvaries with time and position of the pad. The outputs of the padconditioning and wear model are the pad thickness 105, represented by h,and roughness, Preston's coefficient 106, represented by k, which areboth functions of time and position on the pad.

The pressure distribution model 104 predicts the pressure distributionfor a wafer being pressed against a polishing pad. Any type of pressuremodel may be used. In its simplest form, pressure distribution betweenthe pad and a wafer may be modeled as $P = \frac{Force}{Area}$

where the pressure distribution is equal to the downward force of thewafer against the pad over the pad area. Other models can be used, suchas the finite element method model, which isolates the effects of thedeformation of the edges of the polish pad on pressure distribution. Inthe finite element method model for a wafer pressed uniformly againstthe pad, the normal pressure is uniform under the wafer except withinone millimeter of the edge where the pressure increases significantly.The output of the pressure distribution model is a pressure distributionvalue that is used by the pad conditioning and wear model 101 and thewafer scale uniformity model 107.

A wafer scale uniformity model 107 predicts the material removed at eachpoint on the wafer using an enhanced Preston equation. Unlike modelsusing the traditional Preston equation, the enhanced version uses aPreston coefficient 106, k, computed in the pad wear model, thatrepresents pad roughness and varies with time and position on the pad.Pressure distribution on the wafer 104 is also input to the wafer scaleuniformity model. When the simulation of the polishing process firstbegins, each point on the pad starts with an initial value for k. Aspolishing proceeds, the k value at each point is decreased depending onthe amount of polishing performed by that point. In so doing, theuniformity model now captures the semiconductor wafer material ratedrop-off commonly observed in CMP processes and calculates uniformitypredictions 108. Based on other calculations in the wafer scaleuniformity model, throughput for the CMP process is also predicted 108.

A feature-scale planarity model 109 predicts the erosion of features onsemiconductor wafer surfaces using the pad thickness 105, h, computed inthe pad conditioning model that varies with time and position on the padand an erosion rate coefficient E, that varies with position on the pad(and is linked to Preston's coefficient), and stiffness of both the topand base pad Pre-polish topography data 113 is input to the model tosimulate the topography of unpolished wafers. When polishing firstbegins, the top and base pad properties for each point on the pad startwith an initial value. It is known that the stiffness of the top pad isa function of its thickness cubed. It is also known that the base padcompressibility changes with loading. Using the top pad thickness andbase pad compressibility computed in the pad conditioning model, thefeature-scale planarity model predicts how changes in the top padthickness and base pad compressibility along with the loading history ofthe base pad affect planarity 110 and influence pad life.

The pad wear performance predictions 111 use the uniformity andplanarity model results, along with the pad conditioning and wear modelresults to predict pad wear and determine pad life. This is used tooptimize pad life in the CMP process 113. Optimization may beaccomplished in various ways. Pad conditioning and wear performancepredictions can be used to optimize pad life by changing the initial padthickness, including the top pad stiffness or base pad compressibility;by determining the optimal time to roughen or condition the pad tomaintain more constant uniformity results; and by determining theoptimal frequency of conditioning of the pad to extend pad life. Inaddition, CMP process recipe settings may be varied 114, such aschanging the pressure or speed settings of the tool configuration orvarying the geometric configuration of the CMP polish tool such as thepad inner/outer radii and the sweep arm. After optimization hasdetermined various pad parameter changes and optimal recipe settings,the new parameters and settings can be input to the pad conditioning andwear modeling system 100 to repeat the process and determine newuniformity, planarity and throughput predictions based upon the newconfiguration to further optimize and extend pad life. Optimizationallows the user to select any of these variables to vary and torepetitively exercise the pad conditioning and wear modeling system 100.

FIG. 2A is a side-view of a typical Chemical Mechanical Polishing (CMP)tool configuration. FIG. 2B is a top view of a typical ChemicalMechanical Polishing (CM P) tool configuration. In the CMP process, thewafer 201 is affixed to a wafer carrier 202 and pressed face-down on arotating platen 203 holding a polishing pad 205. A slurry feed 206containing an abrasive material held in suspension is dripped onto therotating platen 203 during polish. The carrier 202 and the platen 203rotate at variable speeds, typically on the order of thirty (30) rpm.The tool configuration shown in FIGS. 2A and 2B shows a single-waferpolish tool configuration. Other configurations for polishing multiplewafers exist.

FIG. 3 depicts the decay in material removal rate with polishing time.It is known that the material removal rate provided by a polish paddecreases exponentially with time in the manner depicted in FIG. 3. As aconsequence, the polish pad (205 in FIG. 2B) must be redressed or“conditioned” between polish cycles. Doing so roughens the surface ofthe pad 205 and restores, at least temporarily, its original materialremoval rate. When the pad 205 can no longer be reconditioned, it mustbe replaced.

A flowchart representing the pad conditioning and wear model is shown inFIG. 4. In the pad conditioning and wear model, k (the Prestoncoefficient), is allowed to vary as the pad is conditioned because theconditioning process restores roughness. k also is allowed to vary dueto the amount of polishing performed at each point on the pad. The wearand re-conditioning of the pad process is modeled:

k=k(x,y,t)

The Preston coefficient that varies with time and position on the pad isthen input to the wafer scale uniformity model to form an enhancedPreston equation that calculates wafer uniformity and throughputpredictions. Turning now to FIG. 4, processing starts in the padconditioning and wear model 400 by entering polishing pad and substrateparameters, pad wear model parameters, the number of wafer polish heads,geometric configuration of the polisher tool, and conditioning downforce, pressure distribution between the pad and wafer, along with anyother information needed by the model 401. These values may be inputfrom storage or may be entered by the user via a graphical userinterface to the pad conditioning and wear model program. The values mayalso be determined by previous pad conditioning and wear model systemresults. Optimization allows the user to select any of these variablesto vary and to repetitively exercise the pad conditioning and wearmodeling system 100 as shown in FIG. 1. Minimum and maximumeffectiveness values of the pad represented by k_(g) and k_(c),respectively are two of the parameters needed to be input to the model.

To develop the equations that describe how k changes, it is firstassumed that there is an inherent minimum effectiveness of the pad thatcan be measured. Its minimal effectiveness is represented by a minimumvalue of k, denoted here as k_(g), the g subscript denoting “glazed”. Itis also assumed that there is an inherent maximum effectiveness of thepad that can be measured just after proper conditioning. The maximumvalue of k, which represents the maximum effectiveness, is denoted hereas k_(c), the c subscript denoting “conditioned”. By conditioning thepad, its effectiveness is enhanced and that increase is thereforerepresented by an increase in k. The amount of enhancement is thedifference between k and its minimum value, i.e., k(x,y,t)−k_(g). Ifk(x,y,t)=k_(g), the pad is completely glazed meaning that no furtherwear is possible and the pad is no longer effective. Likewise, ifk(x,y,t)=k_(c) the pad is fully conditioned and further conditioningdoes not improve the pad's effectiveness.

The pad sampling points to be tracked over time are determined 402. Thisprocess is described in further detail in the discussion concerning FIG.5, below. The closer k(x,y,t) is to its maximum value k_(c), the moreeasily it is reduced when in contact with the wafer. Likewise, thecloser k(xmy,t) is to its minimum value, the slower it is reduced whenin contact with the wafer. Based on these arguments, the following padwear model is developed and used to calculate pad degradation and wear403. For a point (x_(p),y_(p)) on the pad, let$\frac{{k\left( {x_{p},y_{p},t} \right)}}{t} = {{- {D_{p}\left\lbrack {{k\left( {x_{p},y_{p},t} \right)} - k_{g}} \right\rbrack}}{P\left( {x_{p},y_{p},t} \right)}{S\left( {x_{p},y_{p},t} \right)}}$

where D_(p) represents the pad degradation rate and is an adjustablemodel parameter. The above model attempts to relate the rate at whichthe pad is degraded (−dk/dt) to its current enhanced effectiveness(k(x,y,t)−k_(g)) times the rate that work (˜PS) is done on its surfaceby the wafer. The next step is to calculate the Preston coefficient, k,that varies with time and position on the pad 404. Note that for thespecial case (fixed point x_(p),y_(p)) under constant wear at pressure Pand speed S, starting with an initial value of k=k_(c), the followingclosed-form solution for calculating roughness which is represented bythe Preston coefficient, k, that varies with time and position on thepad, results:

k(t)=k _(g)+(k _(c) −k _(g))exp[−P·S·D _(p) ·t]

which is of the same form as the data shown in FIG. 3.

Next the pad conditioning model is used to compute the thickness androughness of the pad as a function of time and position on the pad 405.The kinematics and pressure applied during conditioning is used tocompute the amount of material removed at each sampling point. If thepad is completely glazed, that is k(x,y,t)=k_(g), then the rate at whichit is conditioned is highest. As its effectiveness approaches themaximum value k_(c), further conditioning does not help as much. Basedon that simple argument, the conditioning is modeled as$\frac{{k\left( {x,y,t} \right)}}{t} = {{- {D_{c}\left\lbrack {{k\left( {x,y,t} \right)} - k_{c}} \right\rbrack}}{P\left( {x,y,t} \right)}{S\left( {x,y,t} \right)}}$

where D_(c) represents the pad conditioning rate and is an adjustablemodel parameter. The pad thickness is modeled as$\frac{{h\left( {x,y,t} \right)}}{t} = {k_{abrade}{P\left( {x,y,t} \right)}{S\left( {x,y,t} \right)}}$

which states that the rate at which the pad material is removed isproportional to an abrasion constant times the local pressure and therelative velocity.

If all sampling points have been processed 406, the results of the padand wear model simulations are saved 407. These results include the padwear results, the Preston coefficient and the pad conditioning resultsthat computes the thickness of the pad and the amount of materialremoved. If all sampling points have been processed throughout the padconditioning and wear model 406, processing continues at step 403 untilall sampling points are processed.

FIG. 5 shows how the sampling point on a polish pads are interpolated inthe pad conditioning and wear model to determine the Preston coefficientthat varies with time and position on a pad at a wafer sampling point.Turning now to FIG. 5, an array of points 501 on the pad surface 506 isestablished in a way similar to sampling points 502 of the wafer 503.The position and history of these pad sampling points 501 is trackedthrough time, integrating the degradation or restoration equations asthey go. During polishing, the degradation model will be used. In a wayanalogous to modeling wafer overhang during Inside Diameter/OutsideDiameter (ID/OD) processes, when a pad sampling point 501 is not underthe wafer 503, its degradation rate will be dropped to zero by settingD_(p)=0 momentarily. During conditioning, the restoration model will beused. When a pad sampling point 501 is not under the conditioningdevice, its restoration rate will be dropped to zero by setting D_(c)=0momentarily.

The Preston coefficient, the value k, which was once a constant, nowbecomes a value that is interpolated from the rotating grid of padsampling points that lie below the wafer. For any wafer sampling pointi, its x-y position determines four sampling points 505 from whichbilinear interpolation provides a value for k. A search algorithm forfinding the four local pad sampling points 505 and the bilinearinterpolation routine for calculating the Preston coefficient is alsoincluded in the pad conditioning and wear model. The model calculatesand saves the following information:

1.) The positions and current k values of the pad sampling point array.

2.) The number of wafers being polished and the motions of those waferswhile being polished.

3.) The shape of the conditioning device and the conditioning recipe(kinematics and down-force).

The pad conditioning and wear model contains a graphical user interfacefor entering variable data that may be input by the user. The user isable to enter the following process information:

1.) Number of wafers heads running.

2.) Conditioner geometry and recipe.

3.) Parameters describing the pad wear and conditioning model, such asmaximum and minimum pad effectiveness and pad roughness.

The pad conditioning and wear model computes the thickness and roughnessof the polish pad as a function of polish time and position on the pad.The kinematics and pressure applied during conditioning is used tocompute the amount of pad material removed at each point. In FIG. 6, awafer 601 is shown face down in contact with a polish pad 602 having atop pad area 603 that is relatively stiff and a base pad area 604 thatis usually more compressible than the top pad 603. The base pad 604compressibility changes as a function of loading. The top pad 603stiffness is a function of its thickness cubed. The pad conditioning andwear model computes the top pad thickness and base pad compressibilityas a function of time and position on the pad. The top pad stiffness andbase pad compressibility as a function of time and position on the pad,along with the initial top and base pad properties such as thickness andbase pad compressibility before polish action has occurred, are physicalinputs for the feature scale planarity model, which predicts how thechanges in the top pad thickness and base pad compressibility affectplanarity, and hence, pad life.

FIG. 7 shows the planarity model that simulates erosion on thesemiconductor wafer by computing the locally-varying force on the waferby the pad. The erosion of features is equal to the erosion ratecoefficient, computed from the Preston coefficient, times the localforce applied by the pad 701. The local force applied by the pad 701 isdetermined by the local compression of the base pad times the flexuralbending of the top pad. Both the top and bottom pads are represented asa series of springs. The pad 701 and the wafer 702 are discretized(broken up) into nodes (points) 703 and line segments 704 connectingthem. Below each node 703 in the pad is a base spring of compressibilityrk1. The base pad's compressibility is rk1. Below each node 703 in thespring is an auxiliary spring of compressibility rk2. The base pad'sbending rigidity is represented by Hookian springs of strength rk2 thatexert forces within in the pad in proportion to the difference indeflection times the thickness of the pad. At each step during thesimulation, the planarity model determines the amount of wafer-padcontact by requiring a force balance of these springs rk1 and rk2 to besatisfied. Once the contact is determined, the force applied by each padnode 703 onto the associated wear node is used to calculate a materialremoval rate at that point. In this planarity model, top pad thicknessand base pad compressibility as a function of time and position on thepad are input from the pad conditioning and wear model (as described inFIG. 6) to the planarity model. Prepolish wafer topography data is alsoinput to the planarity model as an initial topography. The model canwork from a high-resolution profilometer (HRP) scan to produce theinitial topography or alternatively, arrays of rectangles that describe“up” features on the wafer may be entered by the user. The planaritymodel then uses the topography input data, top pad thickness and basepad compressibility and bulk rate data from the wafer scale uniformitymodel to predict the erosion and hence the planarity of the features onthe wafer after the CMP process. Prior to the pad conditioning and wearmodel that determines pad thickness varying with time and position, theplanarity model used a constant value, h, to represent the thickness ofthe polish pad and therefore did not account for variations in padthickness over the life of the pad in predicting the planarity of thefeatures of the wafer after the CMP process was completed.

The feature scale planarity model used in the present system isdescribed above. Other types of planarity models currently exist. Anyplanarity model that predicts erosion on semiconductor wafers or othertypes of substrates and that can be modified to use changes in polishpad thickness at set sampling points on the pad as a function of timeand position on the pad to determine planarity predictions can besubstituted for the feature scale planarity model used in the presentsystem.

The feature scale planarity model is physically based, and uses the topand base pad properties as direct physical inputs. It is known that thestiffness of the top pad is a function of its thickness cubed, It isalso known that the base pad compressibility changes with loading. Usingthe feature scale planarity model in conjunction with the pad wearmodel, it is possible to predict how changes in the top pad thicknessand the base pad compressibility affect planarity and therefore padlife. Prior to the pad conditioning and wear model, the feature scaleplanarity model described herein used a constant value for the thicknessof the polish pad used in its linear equations for modeling springforce. Since the pad conditioning and wear model computes pad thickness,including top pad stiffness and base pad compressibility varying basedupon the time and position of the pad, the feature scale model in thepresent invention now uses a this a pad thickness value for a set ofsampling points that changes as a function of time and position on thepad in its linear equations for modeling spring force. This produces amore accurate prediction of planarity of the wafer after the CMP processis complete.

FIG. 8 shows typical output displays of the feature scale planaritymodel used in the present invention. An overhead view of a plot of thepre-polish topography 801 is shown under the heading “Up” Features. Theerosion profile 802 shows the predicted planarity results using across-sectional plot of the wafer surface. The pad-wafer interface 803is shown as a cross-sectional plot of the wafer turned upside down andtouching the pad, that is, as it actually appears to the pad.

The wafer-scale uniformity model 107 in FIG. 1, uses the enhancedPreston equation which represents pad roughness as a function of timeand position on the pad to account for pad wear or conditioning. Theuniformity model used in the present system is described below. Othertypes of uniformity prediction models currently exist. Any uniformitymodel that predicts the material removed at each point on the wafer,uses pad roughness as a input to determine those predictions, and can bemodified to use changes in roughness, at set sampling points on the padas a function of time and position on the pad, to determine waferuniformity predictions can be substituted for the uniformity model usedin the present system.

The wafer scale uniformity model used in the present invention statesthat the rate (R) at which material is removed at a point (x_(w),y_(w))on the wafer is proportional to pressure (P) at that point and therelative speed (S) between the wafer and the pad at that point, i.e.,

R(x _(w) ,y _(w) ,t)=kP(x _(w) ,y _(w) ,t)S(x _(w) ,y _(w) ,t).

where k is the Preston coefficient computed in the pad conditioning andwear model that varies with time and position on the pad, P(x_(w),y_(w))is the pressure at that point, and S(x_(w),y_(w)) is the relative speedbetween the wafer and pad at that point. Instead of using the bulkpressure, this slightly enhanced model uses a wafer-centered parabolicpressure distribution, described by the following equation:${P\left( r_{w} \right)} \propto {P_{i} - {\left( {P_{i} - P_{o}} \right)\quad \left( \frac{r_{w}}{R_{wafer}} \right)^{2}}}$

where r_(w) is the radial position on the wafer and P_(i) is a parameterdescribing the pressure at the center of the wafer relative to thepressure P_(o) at the wafer edge. By holding P_(o) constant at 1 andvarying P_(i) and k as fitting parameters, the model is able tofaithfully reproduce experimental results.

FIG. 9 is a flowchart representing pad optimization and determiningoptimal recipe setting (114 in FIG. 1) as performed in the pad wear andconditioning model. Performance requirements for uniformity, planarityand throughput along with the process limitations are entered either bythe user or from a database 900. The pad wear and conditioning modelforms an initial guess for the optimal recipe 901. The number of waferspolished is set to zero 902 to indicate the initiation of the CMPprocess. The polishing of a set of wafers predicting uniformity,planarity, pad wear, pad conditioning and thinning is modeled 903 asshown in FIG. 1. The number of wafers polished is incremented and saved904. If the pad wear performance predictions (111 in FIG. 1) are withinthe specifications of the performance requirements 905, the modeling isrepeated (step 903) until the performance is not within thespecifications. If the performance is not within the specifications, thenumber of wafer polished successfully is output 906. Using a standardoptimization software application program, the number of wafers polishedand the recipe used to polish the wafers, a new solution for the optimalCMP polishing recipe is made 907. If the solution converges 908, anoptimal recipe has been found 909 and processing is complete 910. If thesolution does not converge 908, processing continues at step 902 andrepeats until an optimal recipe is found.

Although the present invention has been described in detail withreference to certain preferred embodiments thereof, other embodimentsare possible. Therefore, the spirit and scope of the appended claimsshould not be limited to the description of the preferred embodimentsherein.

What is claimed is:
 1. A method for modeling, predicting and optimizinga Chemical Mechanical Polishing (CMP) system for polishing semiconductorwafers and other types of substrates used in the manufacture ofintegrated circuits, in a computer program running on a computerprocessor, the method comprising the steps of: a. inputting polishingpad and semiconductor wafer and substrate parameters; b. defining a setof pad sampling points on a CMP polish pad; c. simulating the CMPhardware configuration and inputting CMP system recipe settings; d.using pressure and speed between the wafer and the polish pad; and e.defining a pad wear and conditioning model that predicts the polishingeffectiveness of each sampling point on the polish pad based upon thepolishing pad and substrate parameters, the pressure and speed betweenthe wafer and the polish pad, and on the amount of polishing the pointhas performed in the simulated CMP hardware configuration using the CMPsystem recipe settings, the model comprising i. determining the changein pad roughness for each sampling point on the pad using a pad wearmodel; ii. determining the change in pad thickness for each samplingpoint on the pad using a pad conditioning model.
 2. The method of claim1 wherein pad roughness for each sampling point is represented as a padroughness variable.
 3. The method of claim 2, further comprising: a.defining a set of wafer sampling points on a semiconductor wafer thatcorrespond to the set of pad sampling points; and b. predicting the rateof material removed from the wafer at each wafer sampling point as afunction of the pressure and relative speed between the wafer and thepad at that sampling point, and as a function of the pad roughnessvariable at that sampling point.
 4. The method of claim 2, furthercomprising: a. defining a set of wafer sampling points on asemiconductor wafer that correspond to the set of pad sampling points;and b. using the pad roughness variable for each pad sampling point ascomputed in the pad wear model as an input to a uniformity model, thatpredicts the material removal rate of the material removed from thesurface of a semiconductor wafer at each wafer sampling point.
 5. Themethod of claim 1, the pad conditioning model further comprising: a.representing the polish pad as having a relatively stiff top pad planarsurface connected to and located just above a relatively soft base padplanar surface having a thickness greater than the top pad planarsurface; b. predicting the change in the thickness of the top pad planarsurface for each pad sampling point as a function of the polishing padand substrate parameters, the pressure and speed between the wafer andthe polish pad, the amount of conditioning performed on the top pad, andon the amount of polishing the pad sampling point has performed in thesimulated CMP hardware configuration using the CMP system recipesettings, and determining the resulting thickness of the top pad planarsurface for each sampling point; c. predicting the change in thicknessof the base pad planar surface as a function of the polishing pad andsubstrate parameters, the pressure and speed between the wafer and thepolish pad, and the amount of polishing the pad sampling point hasperformed in the simulated CMP hardware configuration using the CMPsystem recipe settings, and determining the resulting thickness of thebase pad planar surface for each sampling point; and d. using theresulting thickness of the top pad planar surface and the base padplanar surface to compute a pad thickness variable for each samplingpoint.
 6. The method of claim 5, further comprising: a. inputtingpre-polish wafer topography data; b. defining a set of wafer samplingpoints on a semiconductor wafer that correspond to the set of padsampling points; and c. using the pad thickness variable for each padsampling point as computed in the pad conditioning model and thematerial removal rate computed in the uniformity model as an input to aplanarity model for predicting the erosion of features on asemiconductor wafer at each wafer sampling point.
 7. The methodaccording to claim 6, wherein the planarity model is a two-dimensionalplanarity model.
 8. The method according to claim 6, wherein theplanarity model is a three-dimensional model.
 9. The method of claim 1,the pad wear model further comprising: a. representing the polish pad ashaving a relatively stiff top pad planar surface connected to andlocated just above a relatively soft base pad planar surface with athickness greater than the top pad planar surface; b. predicting thechange in the thickness of the top pad planar surface for each padsampling point as a function of the polishing pad and substrateparameters, the pressure and speed between the wafer and the polish pad,the amount of conditioning performed on the top pad, and the amount ofpolishing the pad sampling point has performed in the simulated CMPhardware configuration using the CMP system recipe settings; and c.using the predicted change in thickness to compute a pad roughnessvariable, which represents the roughness of each pad sampling point as afunction of the polishing pad and substrate parameters, the pressure andspeed between the wafer and the polish pad, the amount of conditioningperformed on the top pad planar surface, and on the amount of polishingthe pad sampling point has performed in the simulated CMP hardwareconfiguration using the CMP system recipe settings.
 10. The methodaccording to claim 9, further comprising predicting the throughput forthe CMP process in the uniformity model.
 11. The method according toclaim 1, the pad wear model further comprising: a. representing thepolish pad as having a relatively stiff top pad planar surface connectedto and located just above a relatively soft base pad planar surface witha thickness greater than the top pad planar surface; b. determining aminimum roughness value for the top pad planar surface of the polishpad, which represents the top pad's minimum effectiveness in removingmaterial from a semiconductor wafer during the CMP process; c.determining a maximum roughness value for the top pad planar surface ofthe polish pad, which represents the top pad's maximum effectiveness inremoving material from a semiconductor wafer during the CMP polishingprocess; d. setting an effective roughness value for each sampling pointto the maximum roughness value upon polish process initiation; e.simulating the conditioning process performed on the top pad planarsurface to increase the effective roughness value when the roughnessvalue is less than the maximum roughness value and greater than or equalto the minimum value; and f. predicting and updating the effectiveroughness value for each pad sampling point as it changes during the CMPprocess and conditioning process.
 12. The method according to claim 11,the simulating the conditioning process further comprising: a. computinga polish wear model for each sampling point as a function of a paddegradation rate multiplied by the effective roughness value for eachpad sampling point times the rate the at work is done on the top padplanar surface by the wafer; and b. the rate at which work is done is afunction of the pressure and speed between the wafer and the polish padfor each sampling point during the polishing process.
 13. The methodaccording to claim 12, further comprising: a. computing the pressuredistribution between the pad and the wafer; and b. setting the pressurebetween the wafer and the polish pad for each sampling point to thepressure distribution when the pad is contact with the wafer.
 14. Themethod according to claim 12 using the polish wear model to calculatethe effective roughness value for each sampling point by computing thedifference between the maximum roughness value and the minimum value asa function of the rate at which work is done, and the pad degradationrate over time summed with the minimum effective roughness value. 15.The method according to claim 14, further comprising setting the paddegradation rate to zero when the pad sampling point is not under thewafer.
 16. The method according to claim 15, further comprising settingthe pad restoration rate to zero when the pad sampling point is notunder the conditioning device.
 17. The method according to claim 11,further comprising: a. modeling the pad conditioning process by using apad restoration rate times the effective roughness value for eachsampling point minus the maximum roughness value, times the rate thatwork is done on the top pad surface by the wafer; and b. the rate atwhich work is done is a function of the pressure and speed between thewafer and the polish pad for each sampling point during the polishingprocess.
 18. A method for modeling, predicting and optimizing a ChemicalMechanical Polishing (CMP) system for polishing semiconductor wafers andother types of substrates used in the manufacture of integratedcircuits, in a computer program running on a computer processor, themethod comprising the steps of: a. inputting polishing pad andsemiconductor wafer and substrate parameters; b. defining a set of padsampling points on a CMP polish pad; c. simulating the CMP hardwareconfiguration and inputting CMP system recipe settings; d. usingpressure and speed between the wafer and the polish pad; e. defining apad wear and conditioning model that predicts the polishingeffectiveness of each sampling point on the polish pad based upon thepolishing pad and substrate parameters, the pressure and speed betweenthe wafer and the polish pad, and on the amount of polishing the pointhas performed in the simulated CMP hardware configuration using the CMPsystem recipe settings, the model comprising i. determining the changein pad roughness for each sampling point on the pad using a pad wearmodel; ii. determining the change in pad thickness for each samplingpoint on the pad using a pad conditioning model. f. inputting pre-polishwafer topography data; g. defining a set of wafer sampling points on asemiconductor wafer that correspond to the set of pad sampling points;h. using the pad roughness for each pad sampling point as computed inthe pad wear model as an input to a uniformity model for predicting thematerial removal rate for the material removed from the surface of asemiconductor wafer at each wafer sampling point; and i. using the padthickness variable for each pad sampling point as computed in the padconditioning model and the material removal rate computed in theuniformity model as an input to a planarity model for predicting theerosion of features on a semiconductor wafer at each wafer samplingpoint.
 19. The method according to claim 18, further comprisingoptimizing pad life and determining an optimal CMP recipe setting. 20.The method according to claim 19, the steps of optimizing pad life anddetermining the optimal recipe setting further comprising: a. enteringperformance requirements for uniformity, planarity and throughput; b.forming an optimal recipe solution; c. modeling the polishing of a setof wafers predicting uniformity, planarity, pad wear, pad conditioningand pad thinning; d. performing steps b and c until the model is notwithin the performance requirements entered; e. determining the numberof wafers polished; f. forming a new optimal recipe solution; g.performing steps c through f until the optimal recipe solutionconverges; and h. saving the optimal recipe.
 21. The method according toclaim 20, wherein the entering of performance requirements foruniformity, planarity and throughput is by a user through a graphicaluser interface.
 22. The method according to claim 20, wherein theentering of performance requirements for uniformity, planarity andthroughput is from a previous pad conditioning and wear model systemresult.
 23. The method according to claim 20, further comprisingoptimizing pad life by determining an optimal roughness of the polishpad to both extend pad life and achieve a predetermined uniformity ofthe wafer after the CMP process.
 24. The method according to claim 20,further comprising optimizing pad life by determining an optimal top padstiffness and base pad compressibility to both extend pad life andachieve a predetermined planarity of the wafer after the CMP process.25. The method according to claim 19, further comprising using thepredicted erosion of features and predicted material removed from asemiconductor wafer at each sampling point to predict polish pad wearand determine optimal CMP system parameters including the optimal padparameters, optimal frequency of pad conditioning, geometry of the CMPhardware configuration and CMP recipe settings to optimize polish padlife.
 26. The method according to claim 25, using the predicted polishpad wear to optimize pad life further comprising determining optimalsettings to enhance polish pad life: a. changing polish pad materialproperties; b. changing the polish pad parameters; c. determining anoptimal frequency of conditioning the top pad to maintain constantuniformity; d. changing the CMP process recipe settings; and e. varyingthe simulation of the CMP hardware configuration.
 27. The methodaccording to claim 26, the changing the CMP process setting step furthercomprises: a. varying the pressure between the pad and the wafer duringpolishing; and b. varying the speed between the pad and the wafer duringpolishing.
 28. The method according to claim 25 wherein the optimalsettings to enhance polish pad life are input into the pad conditioningand wear model, uniformity model and planarity model to predict theuniformity and planarity of the wafer after the CMP process.
 29. Themethod according to claim 25, further comprising: a. predicting thedecay in material removal rate during the CMP polish process; b.determining the optimal conditioning frequency of the pad to roughen itssurface and restore the pad's original material removal rate; and c.determining the optimal time of pad replacement.